Narrowband PLC tested for demonstrating PLC characterization

Date of Publication

2016

Document Type

Bachelor's Thesis

Degree Name

Bachelor of Science in Electronics and Communications Engineering

Subject Categories

Electrical and Electronics | Power and Energy

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Ann E. Dulay

Defense Panel Chair

Lawrence Y. Materum

Defense Panel Member

Gerino P. Mappatao
Mark Lorenzo D. Torregoza


Abstract/Summary

The development of powerline channel emulator requires extensive knowledge on techniques in both hardware and software, together with advanced mathematical familiarity, digital signal processing techniques, and of course, a deep understanding on the theory and the concepts of powerline communications. This study presents a method where the narrowband channel emulator can be implemented with the use of a Field-programmable Gate Array (FPGA). The testbed is beneficial to those who wish to study powerline communications and the effect of different types of noise present in a powerline channel in a controlled environment. Further, the study demonstrates a basic estimation of the powerline channel with the use of the Zimmermann model. The channel's capacity clearly exhibits the enormous potential for higher bandwidth communication purposes.

Abstract Format

html

Language

English

Format

Print

Accession Number

TU21500

Shelf Location

Archives, The Learning Commons, 12F, Henry Sy Sr. Hall

Physical Description

246 leaves: colored illustrations; 28 cm.

Keywords

Electric power systems -- Communication systems; Field programmable gate arrays; Electric lines; Power electronics

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