Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer
Date of Publication
2012
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Electronics and Communications Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Cesar A. Llorente
Defense Panel Chair
Roderick Yao Yap
Defense Panel Member
Edwin Sybingco
Bernardo F. So, Jr.
Abstract/Summary
In an attempt to bridge the knowledge gap between the industry and academic community in the field of secondary storage, an implementation of a Serial ATA Host Controller is done on Virtex-4 ML410 after the controller is interfaced to the MicroBlaze softcore processor. The transport and the link layer modules are synthesized and simulated using Verilog in Xilinx Integrated Software Environment (ISE) 13.1. It is then interfaced to the MicroBlaze softcore processor with a system clock of 50 MHz Xilinx Platform Studio (XPS) 12.4. In order to verify results, a module stimulating the hard disk is used. The MicroBlaze acts as the top level controller by providing control inputs to the SATA core and displaying the outputs via the HyperTerminal.
Abstract Format
html
Language
English
Format
Accession Number
TU16856
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
302 leaves ; 28 cm.
Recommended Citation
Chua, K. T., Kong, S. S., & Kua Chun Ming, K. T. (2012). Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/14799
