Reconfigurable ALU for 16-bit DLX based RISC microprocessor core

Date of Publication

2008

Document Type

Bachelor's Thesis

Degree Name

Bachelor of Science in Computer Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Cesar A. Llorente

Defense Panel Chair

Medi A. Nazar

Defense Panel Member

Noriel C. Mallari
Jingel A. Tio

Abstract/Summary

Reconfigurable computing is a computing paradigm that combines the flexibility of software with the speed of hardware. It involves changing the hardware configurations of reconfigurable devices such a Field Programmable Logic Arrays (FPGA), in which the functionality of the logic gates in the programmable devices can be customized.

Dynamic Partial Reconfiguration (DPR) is a type reconfigurability which changes the configuration of a certain portion inside the FPGA at run-time allows for more flexibility, as hardware could be configured and optimized depending on the functionality required.

This research aims to incorporate DPR on a 16-bit DLX-based RISC Microprocessor Core by designing a Reconfigurable Arithmatic Logic Unit (R-ALU) that changes configuration depending on that computational needs of the microprocessor core.

Abstract Format

html

Language

English

Format

Print

Accession Number

TU15460

Shelf Location

Archives, The Learning Commons, 12F, Henry Sy Sr. Hall

Physical Description

1 v. (various foliations) : ill. (some col.) ; 28 cm.

Keywords

Adaptive computing systems; Field programmable gate arrays

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