Designing a Verilog HDL algorithm for the data path and control of a pipelined central processing unit design

College

Gokongwei College of Engineering

Department/Unit

Electronics And Communications Engg

Document Type

Article

Source Title

Engineering Journal

Volume

14

Issue

2

First Page

89

Last Page

103

Publication Date

3-2001

Abstract

The Central Processing Unit (CPU) of a processor takes care of executing instructions from the Instruction Memory (IM). A Pipelined CPU allows several instructions to overlap in execution. This allows the CPU to speed up the process of execution. This paper present an algorithm for "control and data path" HDL modeling of a pipelined CPU. The algorithm for modeling the controller is also presented. Whenever necessary, the controller is capable of stalling the pipeline and it is also capable of forwarding data within the pipeline. A sample program is run and the performance of the controller is analyzed.

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Disciplines

Controls and Control Theory | Theory and Algorithms

Keywords

Motherboards (Microcomputers); Computer algorithms; Pipelining (Electronics)

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