Kaplan-Yorke map Implementation on FPGA for a highly secured image encryption system
Date of Publication
2017
Document Type
Master's Thesis
Degree Name
Master of Science in Electronics and Communications Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Cesar A. Llorente
Defense Panel Chair
Roderick Y. Yap
Defense Panel Member
Reggie C. Gustilo
Elmer R. Magsino
Jonathan R. Dungca
Abstract/Summary
In todays world, where most of the transaction, whether business or personal, is done online, protecting data is of vital importance. In this study, we present a new encryption system utilizing a Chaos map, which is the Kaplan-Yorke map, and implement it on FPGA to create a highly secured image encryption system. Most of the conventional encryption system is designed so as it would have a property of nonlinearity and avalanche effect. But this properties is innate to a system called Chaos. This parallelism of properties lead a lot of researchers into the study of utilizing the chaotic properties of some chaotic maps in data encryption. Most of the researches that take advantage of chaotic property implement it as a software, whereas in this study, we implement the chaotic map in FPGA so as to fully utilize the advantage of hardware-based encryption system and to give way into its VLSI implementation in the near future. Upon implementation and testing of the image output of the said study, it was found that the system offers a high level of security. By this, it could be said, that the future of information technology, particularly on data security, will be safer with the existence of chaos-based encryption systems.
Abstract Format
html
Language
English
Format
Electronic
Accession Number
CDTG007224
Shelf Location
Archives, The Learning Commons, 12F Henry Sy Sr. Hall
Physical Description
1 computer disc ; 4 3/4 in.
Keywords
Data encryption (Computer science); Data protection
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Recommended Citation
Tubola, O. D. (2017). Kaplan-Yorke map Implementation on FPGA for a highly secured image encryption system. Retrieved from https://animorepository.dlsu.edu.ph/etd_masteral/5800