VHDL design of digital time switch
Date of Publication
1995
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Electronics and Communications Engineering
Subject Categories
Electrical and Electronics | Systems and Communications
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Abstract/Summary
The digital time switch is a device that performs switching of time-division multiplexed, pulse code modulated (TDM-PCM) data. The switching functions performed are space division and time division multiplexed data. Switching in time refers to the process of interchanging the information corresponding to two subscribers.Space division switching is achieved by switching informations between two PCM links while time division is achieved by switching the information between different time slots within the same PCM link or channel.The circuitry or design is prototyped using an field programmable gate array (FPGA). The design of the circuit in the FPGA is a venture in Very high speed IC Hardware Description Language (VHDL) that uses a programming language for the input design to the FPGA.The integral element of this thesis is to create a VHDL code design that will be used to program the FPGA to achieve the function of time and space division multiplexed switching.
Abstract Format
html
Language
English
Format
Accession Number
TU06855
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
44 leaves ; Computer printout
Keywords
Time division multiple access
Recommended Citation
Francisco, C., & Quizon, A. (1995). VHDL design of digital time switch. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/3742
Embargo Period
1-17-2021
