A hardware based implementation of neural networks applied to visual pattern recognition
Date of Publication
1995
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Computer Science with Specialization in Computer Technology
College
College of Computer Studies
Department/Unit
Computer Technology
Abstract/Summary
Recent developments in microelectronic technology has diverted the interest of researchers towards hardware implementations of neural networks. The study is directed towards building a simple, small-scale, and fully functional neural network system applied to visual pattern recognition. Processing elements used in implementing the Kohonen algorithm were constructed using available chip components. The software acts as a stand-alone simulation and provides an interface to and from the hardware module and a standard digital computer. The quality of recognition achievable is proportional to the number of neurons and the size of the input channel. Because distance is a relative quantity, deviations due to noise and impedance are inconsequential. Proper normalization and interpretation od data re more significant than the actual values generated. Properly training a neural network to identify a particular set of patterns is a highly heuristic endeavor. Thus, optimizing a map for a specific application requires a thorough understanding of the model, extensive experimentation, and ample training time. Viable neural network solutions in hardware are an attainable reality. However, further study and refinements are still necessary.
Abstract Format
html
Language
English
Format
Accession Number
TU09116
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
97 numb. leaves
Recommended Citation
Abadia, L. B., De Chavez, J. T., Rogando, H., & Sy, A. T. (1995). A hardware based implementation of neural networks applied to visual pattern recognition. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/16599
