FPGA-Based digital image processing development platform to demonstrate JPEG compression using a CMOS image sensor and SD card storage
Date of Publication
2011
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Electronics and Communications Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Edwin Sybingco
Defense Panel Chair
Gerald P. Arada
Defense Panel Member
Roderick Yao Yap
Bernard F. So, Jr.
Abstract/Summary
This paper presents an FPGA based digital image processing platform that demonstrates a JPEG compression. The raw image comes from a CMOS camera module that is attached to the Altera DE2 development board. The compressed image is saved in an SD card after being processed by the hardware implemented image processing algorithms.
The system is composed of two main parts namely the control subsystem and the hardware implemented digital image subsystem. The control system takes care of the data flow, and peripheral interfaces and controllers. The DIP subsystem is implemented in hardware in the FPGA chip which consists of the JPEG compression algorithms.
This study makes use of a System-on-a-programmable-chip (SOPC) system to implement the control system. A programmable Nios II soft processor was also used to serve as the master peripheral for all of the modules in the whole system."
Abstract Format
html
Language
English
Format
Accession Number
TU14663
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Recommended Citation
Cham, P. T., Co, M. D., Dagal, R. C., & Lim, A. Y. (2011). FPGA-Based digital image processing development platform to demonstrate JPEG compression using a CMOS image sensor and SD card storage. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/14443