An FPGA based 16-bit RISC microprocessor core architecture
Date of Publication
2006
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Computer Engineering
Subject Categories
Computer Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Roderick Yap
Defense Panel Member
Nazar, Medi A. Nazar
Jingel A.. Tio
Analene M. Nagayo
Abstract/Summary
Learning fundamentals in designing and implementing a microprocessor is a very critical part on developing such high end systems. This will serve as a strong foundation in designing high-end microprocessors. This thesis which is an FPGA based microprocessor core is a learning tool for the students and future designers. Traditionally, student designers make microprocessors using microcontrollers or the combination of various chips digital converters are not used in making a microprocessor. Also, implementation using integrated circuits through rapid prototyping can limit the design and have trade offs just to have a functioning hardware implementation. Because of this disadvantage, FPGA will be one of the best solutions.
The reconfigurability factor of the FPGA is a very important feature especially in upgrading the microprocessor. Traditional way of implementing microprocessors with discrete components is very tedious than implementing it in FPGA. With an FPGA implementation, students can focus more on the designing of the microprocessor with the performance in mind rather than being limited by the trade offs presented when implemented using discrete components.
This research is an FPGA implementation of a CPU core based on the DLX architecture developed by Hennessy and Patterson. A Virtex-II V2MB1000 FPGA development board was used in the implementation of the microprocessor core which employed pipelining techniques to increase the performance.
Abstract Format
html
Language
English
Format
Accession Number
TU13805
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
1 v. (various foliations) : ill. (some col.) 29 cm
Keywords
Field programmable gate arrays--Computer-aided design; Programmable array logic; Programmable logic devices; Gate array circuits; Microcomputers --Design and construction
Recommended Citation
Cordero, S. G., Gandia, L. J., Lo, R. T., Mendoza, R. C., & Tan, J. S. (2006). An FPGA based 16-bit RISC microprocessor core architecture. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/14286
