Implementation of BIST for an 8-bit SAR ADC on a 0.35um CMOS process
Date of Publication
2011
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Electronics and Communications Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Ann E. Dulay
Defense Panel Chair
Roderick Yao Yap
Defense Panel Member
Maria Antonette C. Roque
Alexander C. Abad
Abstract/Summary
Analog to Digital Converters (ADC) are commonly used in mixed-signal volume circuits. As these circuits become more complex, testing them becomes more difficult especially when they are incorporated in a chip. These circuits should be designed to have the capacity of being tested. This kind of design is called as design for testability (DFT). The use Automated Test Equipment's (ATEs) and Built-in Self Test (BIST) are two ways to test these circuits. Built-in Self Tests are less expensive compared to Automated Test Equipment's. Moreover, BIST enables customers to test ADCs to test faults in the circuit using ordinary test bench equipment's.
The purpose of this study is to implement a BIST for an 8-bit Successive Approximation Register (SAR) ADC. The circuit was implemented on a 0.35 um CMOS process. The BIST system has three parts, the Integral Nonlinearity (INL) detector, Differential Nonlinearity (DNL) detector and the output response analyzer (ORA). These circuits are designed to test static parameters of an 8 bit SAR ADC. These parameters are the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL). The INL and DNL detector circuits are composed of logic gates and ramp generators. The group used ORA to show if the circuit has passed the specifications.
Abstract Format
html
Language
English
Format
Accession Number
TU14736
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
388 leaves: ill. (some col.) 28 cm.
Recommended Citation
Co, C. G., Cresencia, C. C., Natividad, J. O., Wing Siong, K. S., & Yu, A. S. (2011). Implementation of BIST for an 8-bit SAR ADC on a 0.35um CMOS process. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/11789