Design of CMOS based incremental sigma-delta analog-to-digital converter

Date of Publication

2010

Document Type

Bachelor's Thesis

Degree Name

Bachelor of Science in Electronics and Communications Engineering

Subject Categories

Communication | Electrical and Electronics | Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Roderick Yao Yap

Defense Panel Chair

Ann E. Dulay

Defense Panel Member

Miguel O. Gutierrez
Noriel C. Mallari

Abstract/Summary

This paper reviews the theoretical operation and describes the design of a 3.3V CMOS Based Incremental Sigma-Delta Analog-to-Digital Converter using 35um CMOS technology. Incremental sigma-delta analog-to-digital converter is a combination of the Nyquist-Rate Dual Slope Converter and Sigma-Delta Converter that converts analog DC inputs into its corresponding digital output. This analog-to-digital converter contains a voltage reference, switched-capacitor integrator, comparator, 1-bit digital-to-analog converter, and an 8-bit digital counter.

The objective of this thesis is to design an analog-to-digital converter with an INL of less than 10 LSB, and a DNL of less than 5 LSB. This design is limited to converting only positive DC voltage values, and the initial value for the conversion rate is 4ksps. Simulations were done using T-spice and the layout was designed using L-edit.

Abstract Format

html

Language

English

Format

Print

Accession Number

TU15880

Shelf Location

Archives, The Learning Commons, 12F, Henry Sy Sr. Hall

Physical Description

114 leaves : ill. (some col.) ; 28 cm.

Keywords

Analog-to-digital converters

Embargo Period

1-7-2022

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