A VLSI architecture for separable 2-D discrete wavelet transform

Document Type

Article

Source Title

Journal of VLSI Signal Processing

Volume

18

First Page

125

Last Page

140

Publication Date

1998

Abstract

In this paper, an efficient semi-systolic array architecture for separable 2-D Discrete Wavelet Transform (DWT) is introduced. The semi-systolic array is applicable to any convolution that requires an arbitrary subsampling function. The semi-systolic array presents a better implementation of the convolution function of DWT. This kind of implementation offers a higher efficiency compared to regular systolic implementation when applied for 2-D DWT. The architecture has an efficiency of at least 91% which increases proportional to the number of octaves with no change in the architecture design except for minor modifications to the control logic and memory size. The propose architecture is scalable for different size of filter and different number of octave. The communication routing is minimum since data transfers are limited to immediate neighboring processors. The components of the architecture are fairly regular and consist of minimum number of computational units which makes it a good candidate for VLSI implementation.

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Disciplines

Computer Sciences

Keywords

Wavelets (Mathematics); Transformations (Mathematics); Systolic array circuits

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