Flexible architecture for analogue delay line

College

Gokongwei College of Engineering

Department/Unit

Electronics And Communications Engg

Document Type

Article

Source Title

Electronics World

Volume

114

Issue

1871

First Page

35

Last Page

36

Publication Date

11-1-2008

Abstract

The latest circuit provides a flexible architecture for analogue delay lines (ADL), which is useful for both low and high frequencies. The latest design of ADLs, based on the circuit, consists of four basic blocks, such as an analogue-to-digital converter (ADC), a static memory device (SRAM), a digital-to-analogue converter (DAC), and an address counter (AC). The AC provides an extra output bit that is used to toggle the switches. Samples from the ADC are stored in the memory block, which consists of a pair of 15-bit CMOS static RAMs. The addresses of the SRAMs are generated by a cascade of four 4-bit synchronous binary counters. Stored samples are read by a current-mode R-2R ladder DAC that reconstructs a time-delayed version of the analogue input.

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Disciplines

Electrical and Electronics

Keywords

Delay lines; Static random access memory

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