Full-custom design and characterization of a phase locked loop - DLS565 using 0.5um CMOS technology
College
Gokongwei College of Engineering
Department/Unit
Electronics And Communications Engg
Document Type
Conference Proceeding
Source Title
2014 International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management, HNICEM 2014 - 7th HNICEM 2014 Joint with 6th International Symposium on Computational Intelligence and Intelligent Informatics, co-located with 10th ERDT Conference
Publication Date
1-1-2014
Abstract
The DLS565 is a Phase-locked loop (PLL) Integrated Circuit (IC) design project simulated on all process corner libraries (TT, FF, SS, FS, SF) using 0.5um CMOS technology. The final IC design layout of the PLL without bonding pads covers approximately 0.46mm × 0.5mm. The parameters of the DLS565 were measured and compared to the commercially available LM565C and NE565. It operates with a supply voltage of ±2.5 V with a maximum power dissipation of approximately 22 mW. DLS565 was able to capture frequencies as low as 15Hz and as high as 1.12MHz. © 2014 IEEE.
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Digitial Object Identifier (DOI)
10.1109/HNICEM.2014.7016240
Recommended Citation
Atendido, K. C., Co, J. C., Navarro, J. B., Garcia, P. H., & Abad, A. C. (2014). Full-custom design and characterization of a phase locked loop - DLS565 using 0.5um CMOS technology. 2014 International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management, HNICEM 2014 - 7th HNICEM 2014 Joint with 6th International Symposium on Computational Intelligence and Intelligent Informatics, co-located with 10th ERDT Conference https://doi.org/10.1109/HNICEM.2014.7016240
Disciplines
Electrical and Electronics
Keywords
Phase-locked loops; Phase detectors; Voltage-controlled oscillators; Metal oxide semiconductors, Complementary
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