FPGA library based design of a hardware model for convolutional neural network with automated weight compression using K-means clustering
College
Gokongwei College of Engineering
Department/Unit
Electronics And Communications Engg
Document Type
Article
Source Title
International Journal of Advanced Trends in Computer Science and Engineering
Volume
8
Issue
4
First Page
1004
Last Page
1011
Publication Date
7-1-2019
Abstract
In this paper, a design of a synthesizable hardware model for a Convolutional Neural Network (CNN) is presented. The hardware model is capable of self-training i.e. without the use of any external processors. It is trained to recognize four numerical digit images. Another hardware model is also designed for the K-means clustering algorithm. This second hardware model is used to for compressing the weights of the CNN through quantization. Weight compression is carried out through weight sharing. With weight sharing, the system is able to save component usage. The two hardware models designed are then subsequently integrated to automate the compression of the CNN weights after the CNN completes its training. The entire design is based on fixed point arithmetic operation using VHDL as design entry tool and XILINX Virtex 5 FPGA as the target library for synthesis. After completing the design, it is evaluated in terms of hardware consumption with respect to rate of compression. When evaluating the recognition performance ability of the hardware model, digit images experimentation results have shown that the weight compression can reach as high as 60% without any negative effect on the performance of the CNN. Based on data gathered, the compression with the least hardware consumption occurs at 80 %. For the various digits trained, the CNN outputs after the training, range from 89% to 97%. © 2019, World Academy of Research in Science and Engineering. All rights reserved.
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Digitial Object Identifier (DOI)
10.30534/ijatcse/2019/04842019
Recommended Citation
Yap, R., Giron, G., Lanto, L., Garcia, L., Sta. Maria, D., & Materum, L. (2019). FPGA library based design of a hardware model for convolutional neural network with automated weight compression using K-means clustering. International Journal of Advanced Trends in Computer Science and Engineering, 8 (4), 1004-1011. https://doi.org/10.30534/ijatcse/2019/04842019
Disciplines
Electrical and Electronics
Keywords
Field programmable gate arrays; Neural networks (Computer science); Data compression (Computer science); VHDL (Computer hardware description language)
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