FPGA implementation of a didactic GF(2^8) adder

College

Gokongwei College of Engineering

Department/Unit

Electronics And Communications Engg

Document Type

Article

Source Title

Engineering Journal

Volume

16

Issue

1

First Page

59

Last Page

69

Publication Date

9-2003

Abstract

Digital communication systems and digital data storage systems are required to use error control codes. These codes provide the necessary immunity to noise and distortion. One of the most popular linear block codes is the Reed-Solomon (RS) code. To encode and decode the RS code requires a GF(28) adder algorithm, which can be useful for didactic purposes, is discussed and compared with the classical adder algorithm. Both adder algorithms are simulated and synthesized on an XC4025E XILINX Field Programmable Gate Array (FPGA). The classical GF(28) adder requires more gates (> 1000 gates) than the didactic adder. Although the adder is just a portion of the encoders and decoder of RS codes, analysis have been made to show an advantage of the didactic adder over the classical adder. Furthermore, the novel GF(28) adder algorithm can be helpful to students interested in RS codes or BCH codes.

html

Disciplines

Digital Circuits | Theory and Algorithms

Keywords

Field programmable gate arrays; Programmable array logic; Data transmission systems; Computer algorithms

Upload File

wf_no

This document is currently not available here.

Share

COinS