A VHDL model for the ATM header error check

College

Gokongwei College of Engineering

Department/Unit

Electronics And Communications Engg

Document Type

Article

Source Title

Engineering Journal

Volume

12

Issue

1

First Page

60

Last Page

69

Publication Date

9-1998

Abstract

The Cyclic Redundancy Check (CRC) is a highly efficient coding scheme in detecting errors on transmitted data. Conventionally, it is generated by inspecting the data one bit at a time. This may not be feasible for high-speed applications such as Asynchronous Transfer Mode (ATM) switching. A fast way of generating the checksum bits is obtained by parallel feeding of the data. We have designed a VHDL (Very High Speed Integrated Circuit Hardware Description Language) model to implement a parallel CRC that can be used by the AM Header Error Check (HEC). It is a purely combinational circuit that in one clock pulse, or even in the absence of any clock, the checksum bits can be obtained readily. Simulation results have shown that the model satisfies the theoretical expectations. The VHDL model then can be used as the basis for its synthesis for hardware modeling.

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Disciplines

Digital Circuits

Keywords

Logic circuits; Data transmission systems

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