Date of Event
8-27-2021
Location/Venue
via Zoom
Description
Advanced Research Institute for Informatics, Computing and Networking (ADRIC) cordially invited the Lasallian community to the ADRIC Lecture Series Hardware-Software Co-design for Data-Intensive Applications.
Sponsors
Advanced Research Institute for Informatics, Computing and Networking (ADRIC)
Event Type
Lectures and lecturing
Information Source
Help Desk Announcement : August 24, 2021
Keywords
Ann Franchesca Laguna
Recommended Citation
Laguna, A. (2021). Hardware-software co-design for data-intensive applications. Retrieved from https://animorepository.dlsu.edu.ph/events_diary/155
COinS
Comments
About the lecture:
One of the emerging challenges in the Big Data era is that more time and energy is spent in data movement rather than the compute in traditional Von Neumann architecture, where the memory and CPU are separate. This is especially true for data-intensive applications where large amounts of data must be moved from memory to the compute units. Moreover, because of this data movement, the applications' speed is also limited by the communication bandwidth between the memory and the compute units. This limitation is also called the Von Neumann Bottleneck or the memory wall. These applications can be greatly accelerated by (1) increasing the degree of parallelization and by (2) minimizing data movement through in-memory computing. This talk first introduces the idea of in-memory computing and how it can solve the Von Neumann bottleneck. We use a hardware-software co-design approach to accelerate distance-based applications using in-memory computing. In the circuits layer, we utilize Crossbars, Ternary Content Addressable Memories (TCAMs), Multibit-Content Addressable Memories (MCAMs), General Purpose Computing-in-Memory (GP-CiM), and Configurable Memory Arrays (CMA) depending on the required operations of the algorithm and the distance metric. We focus primarily on FeFET-based devices but also present results and comparisons with CMOS-based and ReRAM-based devices. On the application and algorithm side, we focus on few-shot learning, transformer networks, and genetic read mapping. Few-shot learning and transformer networks use attention mechanisms that are inherently memory-bandwidth limited, especially as the system scales. Bioinformatics applications are data-intensive but only require simple operations such as parallel comparisons. Hence, in-memory computing circuits can greatly accelerate bioinformatics applications such as DNA read mapping and assembly.