Date of Publication

5-2022

Document Type

Master's Thesis

Degree Name

Master of Science in Electronics and Communications Engineering

Subject Categories

Electrical and Computer Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics And Communications Engg

Thesis Advisor

Roderick Y. Yap

Defense Panel Chair

Ann E. Dulay

Defense Panel Member

Donabel D. Abuan
Jose Martin Z. Maningo

Abstract/Summary

The aim of this study is to design a CMOS based data-panning algorithm sorter using Tanner Tools and LTSPICE software. Existing data sorter algorithms have circuit implementations with larger circuit components making the data sorting process more power consuming and had difficulties in hardware design implementation. It also aims to design a reconfigurable circuit that allows user to select a number of data to be simulated inside the data-panning based sorter.

The design was able to simulate 8 inputs and be sorted from lowest to highest simultaneously after 8 clock cycles. It has also a minimum hardware component compared to the other data sorter algorithms in terms of multiplexers, data registers, and magnitude comparators. It uses 2*N multiplexers, N*(b+1) data registers, and N/2 magnitude comparators for N represents the number of inputs, while b represents the number of bits of the inputs. A total area of 1.35 mm2 for the entire reconfigurable datapanning sorter circuit using Tanner Tools has been designed with a power consumption of 555 mW and a frequency of 20 μS.

Abstract Format

html

Language

English

Format

Electronic

Keywords

Sorting (Electronic computers); Adaptive computing systems; Metal oxide semiconductors, Complementary

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Embargo Period

11-16-2022

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