Hermon MCP1 die configuration modification (spacer die2 elimination)

Date of Publication

11-2011

Document Type

Master's Thesis

Degree Name

Master of Engineering major in Manufacturing Engineering

Subject Categories

Manufacturing

College

Gokongwei College of Engineering

Department/Unit

Manufacturing Engineering and Management

Thesis Adviser

Nilo T. Bugtai

Defense Panel Chair

Oscar G. Unas

Defense Panel Member

Giovanni L. Fabian
Phyllis L. Lim

Abstract/Summary

Intel Cavite has worked rigorously for Hermon Products to be Site Certified. It has created a team that focused all year long to address all issues encountered along the way. It has also generated solution paths that further improve the process. Hermon MCP1 Die Configuration Modification marks not only one of the most significant developments on this device but more importantly challenged the current design and promotes “out-of-the-box” thinking. Hermon is one of the most complex products that have ever qualified for production at Intel. Hermon process complexity comes from its logic and flash combination merged with a multi-chip package (MCP). This provides cellular customers with functionality that has not been explored before. This also enables the success of Hermon cellular processor to be qualified by Research In Motion (RIM) specifically on its wireless handheld device called Blackberry. Providing this sophisticated device its processing requirement as well as its future product development proves Intel’s goal to be manufacturers of next generation microprocessors. Hermon Site Certified configuration is designed to have a spacer die2 in between TYAX (die1) and SRAM (die2) which is the identified solution path to delamination caused by mold filler intrusion in between these two dies. An innovative solution was identified to replace the essential function of the spacer die in the current Hermon die-stacking configuration. The hard and challenging part is to make the system comparable to the objective of the current process. The solution is established through a long series of experiments, data gathering and analyses. Removing the spacer die significantly simplifies the current assembly process without compromising quality. Process simplification is the best path towards improved manufacturability. It also results to better traceability and maximize resources without acquiring any large cost. This project would also promote essential learning as next generation packages tend to have higher die staking level. Approach truly supports endeavor of the company to further “Leap Ahead” to find and drive novel solution to continue and to strengthen our Best in Class status.

Abstract Format

html

Language

English

Format

Electronic

Accession Number

CDTG006232

Shelf Location

Archives, The Learning Commons, 12F Henry Sy, Sr. Hall

Keywords

Semiconductors—Packing

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Embargo Period

10-3-2023

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