Design and implementation of a low-voltage selectable fractional-order differentiator in a 0.35um CMOS technology

Date of Publication

2014

Document Type

Master's Thesis

Degree Name

Master of Science in Electronics and Communications Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Alexander C. Abad

Defense Panel Chair

Roderick Y. Yap

Defense Panel Member

Ann E. Dulay
Donabel D. Abuan

Abstract/Summary

This study focused on the design and implementation of a selectable fractional-order differentiator (FOD) in a 0.35um CMOS technology operated at 1.5-V supply. In comparison with the works of Gonzales et al. [20] that uses generic microcontroller for switching an FOD from one order to the next, this design of a selectable FOD was realized in an analog microelectronic scale, thus, the physical implementation is relatively smaller. The dimension layout was further reduced by employing reusability of capacitors and resistors. The whole chip layout of the design has a dimension of 11.55mm x 8.32mm or equivalent to a final area of 96.10mm2. The 16 possible orders of an FOD were characterized in terms of its magnitude and phase response in the working bandwidth from 10Hz to 1kHz. Characterization was made for 5 process corner simulations such as tt, ff, ss, sf, and fs using Tanner EDA as the design simulator software and IC layout editor software.

Abstract Format

html

Language

English

Format

Electronic

Accession Number

CDTG005748

Shelf Location

Archives, The Learning Commons, 12F Henry Sy Sr. Hall

Physical Description

1 computer optical disc ; 4 3/4 in.

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