Date of Publication

2005

Document Type

Master's Thesis

Degree Name

Master of Science in Electronics and Communications Engineering

Subject Categories

Electrical and Electronics

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Roderick Y. Yap

Abstract/Summary

Turbo Codes have gained prominence because of its near channel capacity error correcting capability. Bit streams are encoded by concatenating two parallel convolutional encoders, separated by an interleaver. This results to a code, which when transmitted, achieves a very low (almost zero) bit error rate, when observed at the receiver. A more significant characteristic of this encoding/decoding scheme is how these error stricken codes are recovered by the decoder. By utilizing soft decision decoding and an iterative decoding structure, transmitted sequences are recovered with better efficiency. Given these outstanding features, this study presents how a turbo encoder/decoder is implemented on a Field Programmable Gate Array (FPGA) using the Soft Output Viterbi Decoding Algorithm (SOVA). Several models were synthesized and implemented but only two were chosen, one with the fastest speed and the other with the smallest number of gate utilization. A VHDL model was also created for the 25 and 50 bits frame. The designs performance was verified by comparing it with the results obtained from the MATLAB simulation. The decoder's performance was further validated by measuring and comparing the Bit Error Rate (BER) with published results.

Abstract Format

html

Language

English

Format

Electronic

Accession Number

CDTG003973

Shelf Location

Archives, The Learning Commons, 12F Henry Sy Sr. Hall

Physical Description

1 computer optical disc ; 4 3/4 in.

Keywords

Field programmable gate arrays; Programmable logic devices; Coding theory; Turbo codes (Telecommunication)

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