Date of Publication

9-1998

Document Type

Master's Thesis

Degree Name

Master of Engineering major in Electronics and Communications Engineering

Subject Categories

Electronic Devices and Semiconductor Manufacturing

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Roderick Y. Yap

Defense Panel Chair

Lyne R. Palomar

Defense Panel Member

Antonette Camacho
Edwin Sybingco

Abstract/Summary

This practicum project focuses on the minimization of very large system integration (VLSI) test execution times for improving production-mode electrical screening of custom integrated circuits without sacrificing quality. The reduction of test time leads to maximizing profits and minimizing costs. The project aims to fully analyze the Trillium test programs and evaluate its impact on the test execution time and to find out whether or not it has benefit to the company.

Abstract Format

html

Note

Practicum project

Language

English

Format

Electronic

Accession Number

TG03107

Shelf Location

Archives, The Learning Commons, 12F Henry Sy Sr. Hall

Physical Description

52 numb. leaves, 28 cm.

Keywords

Integrated circuits--Very large scale integration; Transputers; Systolic array circuits; Semiconductor industry

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