Branch optimization to improve branch prediction for P6 superpipeline microarchitecture

Date of Publication

1999

Document Type

Master's Thesis

Degree Name

Master of Science in Computer Science

Subject Categories

Systems Architecture

College

College of Computer Studies

Department/Unit

Computer Science

Thesis Adviser

Mitch William Andaya

Defense Panel Chair

Philip Chan

Defense Panel Member

Rene Arellano
Philip B. Casanova

Abstract/Summary

In superpipeline microarchitecture, the instruction execution cycle is divided into many stages. This type of microarchitecture increases the throughput or the number of instructions executed in a certain time period. But, pipeline stalls due to branch misprediction causes severe degradation in the performance. Microarchitecture employs hardware-based branch prediction to predict the branch target. But it is not enough. Software-based or program-level branch prediction is also needed to complement the hardware-based branch prediction. In this paper, rules for branch optimization at program level are introduced to complement the hardware-level branch prediction of P6 microarchitecture.

Abstract Format

html

Language

English

Format

Print

Accession Number

TG03037

Shelf Location

Archives, The Learning Commons, 12F Henry Sy Sr. Hall

Physical Description

1 v. (various foliations) ; 28 cm.

Keywords

Computer architecture; Mathematical optimization; Programming (Electronic Computers)

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