A synthesizable verilog model of an adaptive differential pulse code modulation (ADPCM) codec
Date of Publication
1997
Document Type
Master's Thesis
Degree Name
Master of Science in Electronics and Communications Engineering
Subject Categories
Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Edwin Sybingco
Defense Panel Chair
Roderick Yap,
Defense Panel Member
Roberto T. Caguingin
Enrique Manzano
Abstract/Summary
This thesis proposes to make a Synthesizable Verilog Hardware Description Language (HDL) model of an Adaptive Differential Pulse Code Modulation (ADPCM) codec. The ADPCM model is intended to be used for toll-quality speech compression and would be coded in Verilog HDL's Register Transfer Level (RTL) for synthesizability. Synthesizability assures the designer of the implementability of the design.
Abstract Format
html
Language
English
Format
Accession Number
TG02668
Shelf Location
Archives, The Learning Commons, 12F Henry Sy Sr. Hall
Physical Description
155 numb. leaves
Keywords
Pulse code modulation; Digital electronics; Verilog (Computer hardware description language); Integrated circuits -- Computer simulation
Recommended Citation
Yao, S. U. (1997). A synthesizable verilog model of an adaptive differential pulse code modulation (ADPCM) codec. Retrieved from https://animorepository.dlsu.edu.ph/etd_masteral/1839
