Dynamic hardware based narrowband and wideband channel emulator for modem testing in low-voltage indoor power-line communication scenarios

Ann E. Dulay

Date of Publication

2017

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Electronics and Communications Engineering

Subject Categories

Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Lawrence Y. Materum

Defense Panel Chair

Gerino P. Mappatao

Defense Panel Member

Aaron Don M. Africa
Felicito S. Caluyo
Celso B. Co
Jennifer C. Dela Cruz, .

Abstract/Summary

In this dissertation, a power line communications channel (PLC) emulator that has a random selectivity feature to mimic real-world PLC scenario applied to an indoor network has been designed, developed, tested, and evaluated. The emulator has been implemented in FPGA-based hardware. State-of-the-art PLC channel emulators do not have a random selectivity feature when generating the channels and most of them emulated either the channels only, or the noise only. In this dissertation, the emulator emulates various PLC channels and noise. The performance of the emulator has been compared with the random channel variates generated by PLC channel models. A limiting factor is the number of bits allocated for the fraction part of the fixed-point equivalent of the transfer function.
The results further show that frequency domain operation had effectively speed up the emulation process, and in terms of speed via the number operations per seconds, the developed FPGA emulator is 200% much faster than the simulator.

Abstract Format

html

Language

English

Format

Electronic

Accession Number

CDTG007135

Shelf Location

Archives, The Learning Commons, 12F Henry Sy Sr. Hall

Physical Description

1 computer disc; 4 3/4 in.

Keywords

Communication in engineering; Electronics; Power electronics

This document is currently not available here.

Share

COinS