Design of a 3.3-V rail-to-rail 10-MHz CMOS operational amplifier

Date of Publication

2006

Document Type

Bachelor's Thesis

Degree Name

Bachelor of Science in Electronics and Communications Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Ann Estolano Dulay
Analene Montesines Nagayo

Defense Panel Member

Roderick S. Yap
Antonio S. Gonzales
Roberto T. Caguingin

Abstract/Summary

A 3.3-Volt rail-to-rail 10 MHz operational amplifier (op-amp) is designed using an industry-grade electronic design automation (EDA) tool, i.e. Electric TM, and simulated using WinSpice.

The proposed design makes use of the folded-cascode configuration, which provides the full output swing (rail-to-rail). The design methodology initiates with the following target specifications:

Vdd, Vss = ┴3.3 V

GBW = 10 MHz

Output swing = ┴3.0 V, ┴0.3 V

Gain = 74 dB (5000)

ICMR = ┴2.0 V

Slew rate ≥ 5 V/os

Settling time ≤1 os

Load (cap.) = 20 pF

Phase Margin ≥ 60₀

Min. length = 0.8 om

The mask layout is constructed by adopting the MOSIS CMOS technology, which is available in the EDA tool as mocmossub . The generated layout makes use of two metal layers and one polysilicon.

The simulations performed both for schematic and mask layout include dc analysis, ac analysis, and transient analysis. The results compare well with the design specifications, particularly the rail-to-rail output swing and unity-gain bandwidth.

This study excludes the actual fabrication of the design.

Abstract Format

html

Language

English

Format

Print

Accession Number

TU13787

Shelf Location

Archives, The Learning Commons, 12F, Henry Sy Sr. Hall

Physical Description

1 v. (various foliations) : ill. (some col.) ; 28 cm.

Keywords

Operational amplifiers; Amplifiers (Electronics)

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