FPGA-based built-in self test for a 4-bit BCD adder
Date of Publication
2010
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Electronics and Communications Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Ann E. Dulay
Defense Panel Chair
Roderick Yao Yap
Defense Panel Member
Cesar A. Llorente
Bernardo F. So, Jr.
Abstract/Summary
In this paper, an FPGA-based built in self-test program for a 4-bit BCD adder is presented. The program can detect stuck at faults and bridging faults. The main components of the program include: circuit under test, main controller, test pattern generator, scan chain and the output response analyzer. For the stuck at fault, the main controller controls the test pattern generator which in turn sends out test patterns to the 4-bit BCD adder. In order to test the 4-bit BCD adder, the scan chain is inserted at each stage. The scan chain allows the test patterns to test each node of the BCD adder. The corresponding test output of the system is displayed in the LED’s found within the FPGA board.
For the bridging fault, it cannot be implemented within the FPGA because it is a design rule violation of the FPGA itself, hence an external 2-bit adder circuit is instead constructed. The external circuit is connected to the FPGA, which contains the test pattern for this type of fault. Basically, the VHDL code used to test the stuck-at-faults is also used to test the bridging fault. The stuck-at-fault system detects the errors per node and it can detect varying faults from all nodes simultaneously. All stuck-at-one and stuck-at-zero faults were detected. The bridging fault can detect errors at the input level but detect only one error at a time.
Abstract Format
html
Language
English
Format
Accession Number
TU15886
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
xi, 210 leaves : col. ill.; 28 cm.
Keywords
Field programmable gate arrays; Digital integrated circuits; Electronic digital computers; Electronic circuits--Testing
Recommended Citation
Bergonio, N. B., Halili, R. F., Lim, M. P., & Santiago, C. G. (2010). FPGA-based built-in self test for a 4-bit BCD adder. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/14693