FPGA-based CISC and RISC microprocessor interfacing instructional training module
Date of Publication
2009
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Computer Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Cesar A. Llorente
Defense Panel Chair
Maria Antonette C. Roque
Defense Panel Member
Jingel A. Tio
Oswald L. Sapang
Abstract/Summary
The advancement in microprocessor technology is rapidly increasing everyday. Since we are now in the Pentium age, other microprocessors have become obsolete. Microprocessors today are becoming more powerful, capable of performing faster and bigger tasks than ever before. As a result, microprocessor interfacing becomes harder and more complex. Students taking up courses related to microprocessors, such as computer organization, computer architecture, digital systems design and microprocessor systems, must learn and appreciate the basics of interfacing and architecture of the microprocessors before tackling the recent microprocessors being developed today. The problem is that it is very hard to find 8086-based trainer. RISC based system are becoming the mainstream in providing trainers for RISC processor but they are rather expensive or if not unavailable. This study attempts to provide a flexible training module using FPGA. CISC & RISC architecture can be configured on the FPGA and series of experiments. The training module will consist of five interfacing experiments: (1) the experiment trainer familiarization (memory and parallel port interfacing), (2) keyboard interfacing, (3) VGA monitor interfacing, (4) serial port interfacing and (5) debug monitor program which is an integration of all the interfacing experiments. Students will be provided VHDL microprocessor (one CISC and one RISC) codes to test the interfacing experiments given. Students will also be provided with a lab manual to aid them with the interfacing experiments that they will be doing. Experiments will be done on the Spartan 3E Starter Kit board.
Abstract Format
html
Language
English
Format
Accession Number
TU14862
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
2 v. : ill. (some col.) ; 28 cm.
Keywords
Field programmable gate arrays; Microprocessors; Reduced instruction set computers; Computer architecture; Microprocessors--Design; Pentium (Microprocessor)"
Recommended Citation
Balboa, M. Y., Juan, I. P., Pagalilauan, A. L., & Sy, P. R. (2009). FPGA-based CISC and RISC microprocessor interfacing instructional training module. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/14458