DLS7555: Design and characterization of a 555 timer IC using 0.5um CMOS technology

Date of Publication

2014

Document Type

Bachelor's Thesis

Degree Name

Bachelor of Science in Electronics and Communications Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Alexander C. Abad

Defense Panel Chair

Roderick Yao Yap

Defense Panel Member

Ann E. Dulay
Donabel D. Abuan

Abstract/Summary

From the typical BJT-based designs of the 555 timer, semiconductor companies have also made CMOS-based designs commercially available which made the device to have high noise immunity and low voltage and current rating as compared to its BJT implemented counterparts. The 555 timers CMOS-based topology, however, is barely emerging and must prominently be harnessed as it has a great potential to be a solution to the current and unforeseen predicaments in the field of microelectronics. This paper intends to present the design and characterization process of a 55 Timer IC through the use of the 0.5um CMOS technology and by basing on the specifications of TS555. The study in this paper, however, will only be limited to simulations. The simulation software that will be used in this study is the Tanner EDA tool.

This paper focused on the establishment of a 555 Timer IC using 0.5um CMOS technology. In order to make the 555 Timer IC, the researchers first designed and characterized the devices generic internal components which are basically the voltage divider circuit, compactor opamp, and the SR flip-flop. The comparator opamp, being the most crucial part of the project, was designed and characterized such that it will have a gain of 70 dB. Such a high-gain opamp was designed and characterized since the compactor opamp functions as the principal control circuit of the entire 555 timer. As the optimum design and proper characteristics of these components were achieved, the researchers were able to successfully integrate the components to establish a functional 55 timer.

For further improvements and innovations, the final 555 timer that will be presented in this paper also incorporated the usage of active resistors for the voltage divider circuit. MOS diodes were utilized as active resistors and were designed and characterized such that it would give same performances as the passive resistors. The usage of active resistors saved a total space area of 3898.75 um. A bandgap was also used in the 555 timer for an efficient voltage regulation of the control circuit. This final output in the project is thus entitled as the DLS7555.

The self-established DLS7555 Timer was able to operate at a supply voltage of 1.2 V to 3.3 V at an operating temperature ranging from 0 – 70C. The timer was also able to achieve maximum frequency of 500 KHz and a maximum timing error of 3%.

Abstract Format

html

Language

English

Format

Print

Accession Number

TU18744

Shelf Location

Archives, The Learning Commons, 12F, Henry Sy Sr. Hall

Physical Description

xxvi, 263 leaves : illustrations (some colored) ; 28 cm.

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