Design and implementation of a 1 volt low dropout voltage regulator on a 0.180um CMOS process driving a clock circuit load
Date of Publication
2013
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Electronics and Communications Engineering
Subject Categories
Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Ann E. Dulay
Defense Panel Member
Gerald P. Arada
Donabel D. Abuan
Abstract/Summary
The main purpose of this research is to design a low dropout voltage regulator (LDO) on 0.18um CMOS process with a maximum dropout of 500mV at a maximum load current of 500uA current. The specifications of this block are based on its application to regulate the clock circuit of a smart wire chip, which serve as the load. The clock circuit load mentioned above ranges from 100KHz to 7.2MHz. The main component of this block is a folded cascode amplifier that functions as an error amplifier with a PMOS pass transistor that operates mainly at its linear region to function as a resistive device. The error amplifier with a reference value of 0.8V outputs a specific value to drive the gate of the pass transistor to produce a specific resistance value between the drain and the source to correct the output value to 1V not exceeding the allowable ripple voltage of 100mV given the input voltage of 1.5V 100mV ripple.
The design satisfies the above conditions on all process corners and is implemented using the SYNOPSYS custom designer schematic and layout tool. The circuit has an efficiency of 34.23% a load regulation of 1.1%, and an accuracy of 97.90% all measured at typical-typical. These parameters are measured in pre-layouts, post-layout on all process corners.
Abstract Format
html
Language
English
Format
Accession Number
TU18208
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
vi, 126 unnumbered leaves :illustrations (some colored) ; 28 cm.
Keywords
Voltage regulators Metal oxide semiconductors, Complementary
Recommended Citation
Lim, J. S., Maranan, J. G., & So, A. G. (2013). Design and implementation of a 1 volt low dropout voltage regulator on a 0.180um CMOS process driving a clock circuit load. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/11534
