Inter-integrated circuit (I²C) design of Zilog's z8 Encore! XP®
Date of Publication
2011
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Electronics and Communications Engineering
Subject Categories
Communication | Electrical and Electronics | Engineering
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Roderick Yap
Defense Panel Chair
Bernardo F. So, Jr.
Defense Panel Member
Ann E. Dulay
Alexander C. Abad
Abstract/Summary
This paper reviews the theoretical operation and describes the design of a Inter-Integral Circuit (I2C) using 0.25um CMOS technology. 12C is a communication tool used to communicate between peripheral devices. It is composed OF 2 bidirectional buses/lines namely the SCL and SDA lines. The different control signal passes through these lines to establish an operation between the master and the slave. The 12C configuration could be a MASTER-SLAVE mode, MASTER mode or SLAVE MODE.
The I2C module design aims to mimic the behavior of I2C module of Zilog's Z8 Encore! XP® F64XX Series Development Kit. This design is limited only to 8-bit data transfer application and tested only using a 4k EEPROM (AT24C04) as a slave. This design only dealt with the MASTER mode configuration of the I2C.
Abstract Format
html
Language
English
Format
Accession Number
TU14733
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
181 [220] leaves: ill (some col.) ; 28 cm.
Keywords
Zilog Z-80 (Microprocessor); Digital integrated circuits--Design and construction
Recommended Citation
Carino, F. R., Malubay, M. V., Rama, N. P., & Ramirez, D. D. (2011). Inter-integrated circuit (I²C) design of Zilog's z8 Encore! XP®. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/10688
Embargo Period
1-7-2022
