An FPGA-based 8-bit 8051 compatible microcontroller

Date of Publication

2014

Document Type

Bachelor's Thesis

Degree Name

Bachelor of Science in Electronics and Communications Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics and Communications Engineering

Thesis Adviser

Roderick Y. Yap

Defense Panel Chair

Alexander C. Abad

Defense Panel Member

Donabel D. Abuan
Ann E. Dulay

Abstract/Summary

The study is about the development of an FPGA-Based 8-Bit 8051 Compatible Microcontroller architecture for the External Parallel and Serial Interfacing Blocks, implemented in Virtex-5. Additional features for the existing 8051 Microcontroller Core done by the previous proponents were developed. Additional features were also coded specifically the UART, IO Interface, Timer Circuit, and Interrupt Function separately using Verilog before integrating all of it into the 8051 core. After the researchers incorporated the additional features to the 8051 core, they implemented and synthesized it using Xilinx ISE. Simulation through the ISim simulator verified the features of the functions. After the verification of the expected output of the design, the actual testing were performed by implementing the program itself into a Virtex-5 FPGA Board. The researchers used a 4x4-Matrix Keypad, Address Counter, and the LCD Interface of the Virtex-5 to program the Read Only Memory (ROM) module of the 8051 core. The researchers also used a Spartan-3E Evaluation Board and an external circuit with LEDs during the actual testing of the FPGA-based Microcontroller to the outside world to verify the performance of all the additional features completed. Aside from the Spartan-3E Evaluation Board, the Virtex-5 was also able to communicate with the actual 8051 Microcontroller (AT89C4051) using the serial port (UART).

Abstract Format

html

Language

English

Format

Print

Accession Number

TU18754

Shelf Location

Archives, The Learning Commons, 12F, Henry Sy Sr. Hall

Physical Description

xv, 99 leaves : illustrations (some colored) ; 28 cm.

Keywords

Field-programmable gate array

Embargo Period

12-7-2021

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