Experimental modules on integrated circuit design using tanner for 0.25 um, 0.35 um, and 0.5 CMOS process
Date of Publication
2010
Document Type
Bachelor's Thesis
Degree Name
Bachelor of Science in Electronics and Communications Engineering
Subject Categories
Psychology
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Roderick Y. Yap
Defense Panel Chair
Cesar A. Llorente
Defense Panel Member
Ann E. Dulay
Bernardo F. So, Jr.
Abstract/Summary
The purpose of this study was to make an Experimental Modules on Integrated Circuit Design Using Tanner for 0.35 um, and 0.5 um CMOS Process. The study includes the development of the environment library for the 0.25 um, 0.35 um, and 0.5 um CMOS processes and the construction, layout designing, DRC, LVS, Parasitic Extraction, and simulation of the circuits. The study also focuses the development of tutorial manuals for using the different designing tools of Tanner EDA, namely, L-Edit and S-Edit, in 0.25 um, 0.35 um CMOS Processes designing environment.
Abstract Format
html
Language
English
Format
Accession Number
TU14732
Shelf Location
Archives, The Learning Commons, 12F, Henry Sy Sr. Hall
Physical Description
114[127] leaves: ill. (some col) ; 28 cm.
Keywords
Integrated circuits--Design and construction; Digital integrated circuits--Design and construction
Recommended Citation
Escano, R. V., Katigbak, B. S., Kumar, N. P., & Santiago, J. G. (2010). Experimental modules on integrated circuit design using tanner for 0.25 um, 0.35 um, and 0.5 CMOS process. Retrieved from https://animorepository.dlsu.edu.ph/etd_bachelors/10455
Embargo Period
11-24-2021
