Date of Publication


Document Type

Master's Thesis

Degree Name

Master of Science in Mechanical Engineering

Subject Categories

Mechanical Engineering


Gokongwei College of Engineering


Mechanical Engineering

Thesis Advisor

Aristotle T. Ubando

Defense Panel Chair

Martin Ernesto L. Kalaw

Defense Panel Member

Jeremias A. Gonzaga
Vicente DyReyes


Fan-out wafer-level packaging has now become one the most widely used approaches for microelectronic component system integration using system-in-package because of its potential packaging size and electrical performance advantages. It is typically manufactured by embedding the silicon chips with epoxy molding compound while in wafer level and then redistributed layers of copper were fabricated which are also embedded in polyimide thin films instead of conventional substrate. During these processes, the package experiences large temperature variations which may lead to internal stresses and interfacial delamination caused by a large thermal expansion mismatch. In this study, the potential interfacial delamination on the fan-out wafer-level package was analyzed using the finite element method. A definitive screening design was employed to screen the factors that significantly affect the potential interfacial delamination on the individual package of fan-out wafer-level package when subjected to a thermal load. And then using a response surface design, the influence of significant factors on the potential interfacial delamination was further analyzed using prediction profilers and contour plots. The finite element models were validated and found to be in good agreement with the existing warpage measurements from the literature. The results of finite element analysis through virtual crack closure technique and design of experiments show that the factor that influence the interfacial delamination the most was the coefficient of thermal expansion of epoxy molding compound above its glass transition temperature. Increasing this coefficient of thermal expansion increases the possibility of interfacial delamination at the interface of epoxy molding compound and Silicon chip and even exceeds the critical energy release rate.

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