Development of speech activated Servo motor controller in FPGA
Date of Publication
3-2011
Document Type
Master's Thesis
Degree Name
Master of Science in Electronics and Communications Engineering
Subject Categories
Electrical and Electronics
College
Gokongwei College of Engineering
Department/Unit
Electronics and Communications Engineering
Thesis Adviser
Edwin Sybingco
Roderick Y. Yap
Defense Panel Chair
Cesar A. Llorente
Defense Panel Member
Rodrigo S. Jamisola Jr.
Enrique M. Manzano
Abstract/Summary
Speech recognition systems have been developed in the past. Various technologies have been used including Field Programmable Gate Array (FPGA). With this research, it is the authors’ main objective to develop in a single FPGA a servo motor controller that is activated using speech commands, namely, stop, clockwise and counterclockwise. The software model that was used as a blueprint in the FPGA implementation was done in MATLAB. Besides being the basis for the FPGA design, the MATLAB model was also used for getting the various speech parameters that were then inputted to the FPGA for speech recognition. FPGA implementation was then made using hardware description language (HDL) in 2 major parts: 1) speech recognition system including the speech acquisition module and 2) servo motor controller pulse width modulation (PWM) system. Afterwards, the system was tested for recognition accuracy using an acoustics laboratory with sound-proofing materials to minimize noise. With 200 samples each word, the commands stop, clockwise and counterclockwise had 100.00%, 98.00% and 100.00% accuracy respectively versus the research minimum objective of 70% per command.
Abstract Format
html
Language
English
Format
Electronic
Electronic File Format
MS WORD
Accession Number
CDTG004931
Shelf Location
Archives, The Learning Commons, 12F Henry Sy Sr. Hall
Physical Description
1 computer optical disc. ; 4 3/4 in.
Keywords
Field programmable gate arrays
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Recommended Citation
Marquez, R. N. (2011). Development of speech activated Servo motor controller in FPGA. Retrieved from https://animorepository.dlsu.edu.ph/etd_masteral/7136
Embargo Period
4-25-2022