Title

A heuristic approach in the characterization of JFET functionality

Date of Publication

2003

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Electronics and Communications Engineering

Subject Categories

Electrical and Electronics

College

Gokongwei College of Engineering

Department/Unit

Electronics And Communications Engg

Thesis Adviser

Felicito Caluyo

Defense Panel Chair

Felixberto Cruz

Defense Panel Member

Elmer Dadios
Alvin Chua
Edwin Calilung
Harry Joson

Abstract/Summary

The process flow and the recipes for production used in the fabrication of integrated circuit devices are always adjusted depending on the type of device one wants to produce. The whole process requires extensive characterization activities to match the different fabrication process parameters with the desired device performance. Any shifts in the fabrication process would result to variations in the resulting device performance. The study aims to develop a methodology for JFET characterization. This characterization method will be used as a major tool in predicting JFET functionality. Such methodology will take into consideration the most essential elements that govern the functionality of a JFET device. This method utilizes data obtained at wafer level to effectively predict JFET back-end functionality. The methodology will be combined with appropriate simulations consistent with the characterization of the device. The results are compared with the actual yield. The new method closely reflects observed phenomena and takes into account the complex interactions between the various parameters.

Abstract Format

html

Language

English

Format

Print

Accession Number

TG03436

Shelf Location

Archives, The Learning Commons, 12F Henry Sy Sr. Hall

Physical Description

228 numb. leaves ; 28 cm.

Keywords

Junction transistors; Tunnel diodes; Electric current rectifiers; Semiconductors -- Junctions

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