A heuristic approach in the characterization of JFET functionality
Date of Publication
Doctor of Philosophy in Electronics and Communications Engineering
Electrical and Electronics
Gokongwei College of Engineering
Electronics And Communications Engg
Defense Panel Chair
Defense Panel Member
The process flow and the recipes for production used in the fabrication of integrated circuit devices are always adjusted depending on the type of device one wants to produce. The whole process requires extensive characterization activities to match the different fabrication process parameters with the desired device performance. Any shifts in the fabrication process would result to variations in the resulting device performance. The study aims to develop a methodology for JFET characterization. This characterization method will be used as a major tool in predicting JFET functionality. Such methodology will take into consideration the most essential elements that govern the functionality of a JFET device. This method utilizes data obtained at wafer level to effectively predict JFET back-end functionality. The methodology will be combined with appropriate simulations consistent with the characterization of the device. The results are compared with the actual yield. The new method closely reflects observed phenomena and takes into account the complex interactions between the various parameters.
Archives, The Learning Commons, 12F Henry Sy Sr. Hall
228 numb. leaves ; 28 cm.
Junction transistors; Tunnel diodes; Electric current rectifiers; Semiconductors -- Junctions
Lim, F. C. (2003). A heuristic approach in the characterization of JFET functionality. Retrieved from https://animorepository.dlsu.edu.ph/etd_doctoral/918