MIXTO: MIPS-to-x86 translator and optimizer

Date of Publication


Document Type

Bachelor's Thesis

Degree Name

Bachelor of Science in Computer Science

Subject Categories

Computer Sciences


College of Computer Studies


Computer Science

Thesis Adviser

Roger Luis T. Uy

Defense Panel Chair

Clement Y. Ong

Defense Panel Member

Macario O. Cordel II
Ann Franchesca B. Laguna


Along with the rise of various computer technologies, programming has always been an essential component. In retrospect, programmers deal with various issues such as hardware-software compatibilities and code optimization. This is because different hardware processors have their own instruction set architecture (ISA) which basically dictates the programming of its hardware. Considering this, tools for programming and optimization have been of interest. There have also been other tools such as software emulators and simulators that attempts to increase the compatibility between different hardware. In the architectural design of processors, when comparing two different architectures in a certain characteristics, specifically their ISA, reduced instruction set computers (RISC) and complex instruction set computers (CISC) have a wide difference. This is because each architecture is designed with a different principle in mind. In addition, the inherent microarchitecture and hardware implementation for each architectural principle, RISC and CISC, also varies. Both architectural principles have a market that it dominates. RISC dominates the mobile computing market while CISC dominates the desktop market. Recently however, both are penetrating to the other's market. This merging of markets suggests software compatibility between the architectures. Software compatibility can mean translation of programs from one processor to the other. Being that each processor architecture has both its own ISA and a principle for this ISA, code written for an architecture cannot be simply ported to another. Thus the aim of this study is to provide a means of porting software between architectures of different design principles, RISC and CISC. A MIPS64 to x86_64 translator with few to non-existent errors were developed, limited however only to the EduMIPS64 simulator instruction set. A MIPS64 register renaming optimizer as well as a loop unrolling optimizer based on cliche detection were developed but with limitations. A similar loop unrolling optimizer was also developed for x86_64 code.

Abstract Format






Accession Number


Shelf Location

Archives, The Learning Commons, 12F, Henry Sy Sr. Hall

Physical Description

x, 183 pages: illustrations (some colored); 28 cm.


Computer architecture; MIPS (Computer architecture); X86 assembly language (Computer program language)

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