Title

A VHDL implementation of an enhanced reconfigurable arithmetic logic unit implemented in Virtex 4

Date of Publication

2011

Document Type

Thesis

Degree Name

Bachelor of Science in Computer Engineering

Subject Categories

Electrical and Computer Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics And Communications Engg

Thesis Adviser

Bernardo So, Jr.

Defense Panel Chair

Cesar Llorente

Defense Panel Member

Gerald Arada
Elmer Magsino

Abstract/Summary

Reconfigurable computing has been a computing method that further develops the processing speed of the software. It drastically increases the computing speed depending on the implementation and the hardware specifications. It requires manipulation of the hardware configurations in reconfigurable devices in which Field Programmable Logic Array (FPGA) is one of the several devices that are capable of doing reconfiguration. With reconfiguration, the functionality of the logic gates in the programmable devices can be customized to further improve the computation speed.

The implementation of a reconfigurable Arithmetic Logic Unit (RALU) can be done in microprocessors. However, the real application of the implemented RALU can best be seen and use through interfacing in Input/output (I/O) devices such as keyboard, Video Graphics Array (VGA) monitor. With such implementation and interface, it can serve as a standalone computer.

This research aims to integrate the implemented RALU of Cardenas, et al. and the I/O interface by designing an I/O interface by designing an I/O module that can use the RALU and be utilized to the user's application.

Abstract Format

html

Language

English

Format

Print

Accession Number

TU14728

Shelf Location

Archives, The Learning Commons, 12F, Henry Sy Sr. Hall

Physical Description

118 leaves, 28 cm.

Keywords

Adaptive computing systems

Embargo Period

4-12-2021

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