Title

CAI for microprocessor architecture and design of RISC architecture

Date of Publication

2007

Document Type

Thesis

Degree Name

Bachelor of Science in Civil Engineering

Subject Categories

Electrical and Computer Engineering

College

Gokongwei College of Engineering

Department/Unit

Electronics And Communications Engg

Thesis Adviser

Medi A. Nazar

Defense Panel Chair

Oswald L. Sapang

Defense Panel Member

Jingel A. Tio
Cesar A. Llorente

Abstract/Summary

This project entitled CAI FOR MICROPROCESSOR ARCHITECTURE AND DESIGN OF RISC ARCHITECTURE is a web-based educational tool that aims to enhance the knowledge of the user in microprocessor architecture and the design of the Reduced Instruction Set Computer Architecture. This project was developed using PHP as the middleware and MySQL for the database. Macromedia Flash was used in creating the lecture pages to be able to incorporate relevant interactions, simulations and animations in the discussion. These means are effective in imparting knowledge to the user and were also proven by the results undertaken.

Abstract Format

html

Language

English

Format

Print

Accession Number

TU13952

Shelf Location

Archives, The Learning Commons, 12F, Henry Sy Sr. Hall

Physical Description

1 volume (various foliations), illustrations (some color), 28 cm

Keywords

Microprocessors; Computer architecture

Embargo Period

3-17-2021

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